The formation of lattice-mismatched materials has many practical applications. For example, germanium (Ge) heteroepitaxy on silicon (Si) is promising both for, e.g., high-performance Ge p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and as a potential path for integrating optoelectronic devices with Si complementary metal-oxide semiconductor (CMOS) technology. Heteroepitaxially growing Ge on Si also is a path for providing a substitute for Ge wafers for many other applications such as photovoltaics and light-emitting diodes, provided that a sufficiently high-quality Ge surface can be obtained cost-effectively. Unfortunately, growing more than a few nanometers (nm) of Ge directly on Si can lead to a dislocation density of 108-109/cm2 due to the 4.2% lattice mismatch, which is unacceptable for most applications. Various solutions involving thick epitaxial layers (most successfully to date via graded-buffer technology) or post-growth high-temperature annealing have been explored to alleviate this problem. However, for true ease of integration with Si CMOS technology, a defect reduction solution involving low epitaxial layer thickness (to meet planarity requirements for Si processing) and low thermal budget (to allow addition of Ge at any point in the process without degrading the CMOS transistor elements) is highly desirable.